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SMPS MOSFET
PD - 94384A
IRFPS40N60K
Applications l Hard Switching Primary or PFC Switch l Switch Mode Power Supply (SMPS) l Uninterruptible Power Supply l High Speed Power Switching l Motor Drive Benefits Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current l Enhanced Body Diode dv/dt Capability Absolute Maximum Ratings
l
HEXFET(R) Power MOSFET
VDSS
600V
RDS(on) typ.
0.110
ID
40A
SUPER TO-247AC
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case )
Max.
40 24 160 570 4.5 30 7.5 -55 to + 150 300
Units
A W W/C V V/ns
C
Avalanche Characteristics
Symbol
EAS IAR EAR
Parameter
Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
600 40 57
Units
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.24 ---
Max.
0.22 --- 40
Units
C/W
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1
10/20/04
IRFPS40N60K
Static @ TJ = 25C (unless otherwise specified)
Symbol V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) IDSS IGSS
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage
Min. Typ. Max. Units Conditions 600 --- --- V VGS = 0V, ID = 250A --- 0.63 --- V/C Reference to 25C, ID = 1mA --- 0.110 0.130 VGS = 10V, ID = 24A 3.0 --- 5.0 V VDS = V GS, ID = 250A --- --- 50 VDS = 600V, VGS = 0V A --- --- 250 VDS = 480V, VGS = 0V, TJ = 125C --- --- 100 VGS = 30V nA --- --- -100 VGS = -30V Min. 21 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 47 110 97 60 7970 750 75 9440 200 260 Max. Units Conditions --- S VDS = 50V, ID = 24A 330 ID = 38A 84 nC VDS = 480V 150 VGS = 10V, See Fig. 6 and 13 --- VDD = 300V --- ID = 38A ns --- RG = 4.3 --- VGS = 10V,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 480V, = 1.0MHz --- VGS = 0V, VDS = 0V to 480V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Symbol IS
ISM
Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Diode Characteristics
Min. Typ. Max. Units Conditions D --- --- 40 MOSFET symbol showing the A G --- --- 160 integral reverse S p-n junction diode. --- --- 1.5 V TJ = 25C, IS = 38A, VGS = 0V --- 630 950 TJ = 25C IF = 38A ns --- 730 1090 TJ = 125C di/dt = 100A/s --- 14 20 TJ = 25C C --- 17 25 TJ = 125C --- 39 58 A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VSD trr Qrr IRRM ton Notes:
Repetitive rating; pulse width limited by
max. junction temperature.(See Fig. 11)
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25C, L = 0.84mH, RG = 25,
IAS = 38A, (See Figure 12a)
ISD 38A, di/dt 224A/s, VDD V(BR)DSS,
TJ 150C
R is measured at TJ approximately 90C
2
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IRFPS40N60K
1000
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
ID, Drain-to-Source Current (A)
10
ID, Drain-to-Source Current (A)
100
10
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1
4.5V
1
0.1
4.5V
0.01
20s PULSE WIDTH Tj = 25C
0.001 0.1 1 10 100 0.1 0.1 1
20s PULSE WIDTH Tj = 150C
10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.5
I D = 38A
3.0 100
T J= 150 C
R DS(on) , Drain-to-Source On Resistance
I D, Drain-to-Source Current (A)
2.5
10
(Normalized)
2.0
1
TJ = 25 C
1.5
1.0
0.1
0.5
V DS= 50V 20s PULSE WIDTH 0.01 4 6 8 10 11 13 15
V GS = 10V
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
V GS Gate-to-Source Voltage (V) ,
TJ , Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFPS40N60K
100000
VGS C iss C rss C oss = 0V, f = 1 MHZ =C +C , C SHORTED gs gd ds =C gd =C +C ds gd
12
I D = 38A
VDS = 480V VDS = 300V VDS = 120V
10
10000
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Ciss
7
1000
Coss
100
5
Crss
2
10 1 10 100 1000
0 0 50 100 150 200 250
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100
ID, Drain-to-Source Current (A)
100
I SD , Reverse Drain Current (A)
10
T J= 150 C
10
100sec 1msec
TJ = 25 C
1
1 10msec Tc = 25C Tj = 150C Single Pulse 1 10 100 1000 10000
V GS = 0 V
0.1 0.2 0.6 0.9 1.3 1.6
0.1
V SD ,Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFPS40N60K
40
V DS VGS
RD
30
RG 10V
D.U.T.
+
-VDD
I D , Drain Current (A)
20
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
10
VDS 90%
0 25 50 75 100 125 150
TC , Case Temperature
( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
1
(Z thJC )
D = 0.50 0.1 0.20
Thermal Response
0.10 0.05 0.01 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.001 0.00001 0.0001 0.001 0.01 t1/ t 2 +TC 1
J = P DM x Z thJC
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPS40N60K
1200
ID
5.0
VGS(th) Gate threshold Voltage (V)
TOP
960
17A 24A 38A
4.5
BOTTOM
EAS , Single Pulse Avalanche Energy (mJ)
4.0
720
ID = 250A
3.5
480
3.0
240
2.5
0 25 50 75 100 125 150
2.0
Starting Tj, Junction Temperature ( C)
-75
-50
-25
0
25
50
75
100
125 150
T J , Temperature ( C )
Fig 12a. Maximum Avalanche Energy Vs. Drain Current
Fig 14. Threshold Voltage Vs. Temperature
15V
V(BR)DSS
VDS L
DRIVER
tp
RG
20V
D.U.T
IAS tp
+ - VDD
A
0.01
I AS
Fig 12b. Unclamped Inductive Test Circuit
Current Regulator Same Type as D.U.T.
Fig 12c. Unclamped Inductive Waveforms
50K 12V .2F .3F
QG
VGS V
D.U.T. + V - DS
QGS
QGD
VGS
3mA
VG
IG
ID
Current Sampling Resistors
Charge
Fig 13a. Gate Charge Test Circuit
Fig 13b. Basic Gate Charge Waveform
6
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IRFPS40N60K
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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IRFPS40N60K
SUPER TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
0.13 [.005] 16.10 [.632] 15.10 [.595] 5.50 [.216] 4.50 [.178] 2.15 [.084] 1.45 [.058] 0.25 [.010] 13.90 [.547] 13.30 [.524] BA A
2X R 3.00 [.118] 2.00 [.079]
1.30 [.051] 0.70 [.028] 20.80 [.818] 19.80 [.780] 4 16.10 [.633] 15.50 [.611] 4
C 1 2 3 B 14.80 [.582] 13.80 [.544] O 1.60 [.063] MAX. E E
4.25 [.167] 3.85 [.152]
5.45 [.215] 2X
3X
1.60 [.062] 1.45 [.058] BA
3X
1.30 [.051] 1.10 [.044]
0.25 [.010]
2.35 [.092] 1.65 [.065] S ECT ION E-E NOTES : 1. DIMENS IONING AND TOLERANCING PER AS ME Y14.5M-1994. 2. DIMENS IONS ARE S HOWN IN MILLIMETERS [INCHES ] 3. CONT ROLLING DIMENS ION: MILLIMETER 4. OUTLINE CONFORMS T O JEDEC OUT LINE T O-274AA
LEAD AS S IGNMENT S MOS FET 1 - GAT E 2 - DRAIN 3 - S OURCE 4 - DRAIN IGBT 1 - GATE 2 - COLLECT OR 3 - EMIT T ER 4 - COLLECT OR
Super-247TM Part Marking Information
EXAMPLE: THIS IS AN IRFPS37N50A WITH ASSEMBLY LOT CODE A8B9 INTERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE
IRFPS37N50A
PART NUMBER
A8B9
0020
TOP
DATE CODE (YYWW) YY = YEAR WW = WEEK
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.10/04
8
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